Electronics and Communication Engineering

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A Low-Power Analog Front End Circuits for Portable Bio-Medical Devices
(National Institute of Technology, Silchar, 2026) Prasad, Ronanki Sai
Application of Generative AI in Automated and LLM-Judged C/SystemVerilog/UVM Test Code Generation
(National Institute of Technology, Silchar, 2026) Gangrade, Kaustubh
The engineering of modern VLSI systems-on-chip is becoming increasingly constrained by a single step: verification. This stage is the major cause of schedule delays as well as cost overstretches. Due to the growing use of heterogeneous architecture in chips, the tedious work of writing and maintaining tests has been a major scaling issue. This problem is overcome by the current thesis that produces the pipeline that automates the test case generation. Instead of starting with a blank slate the system will build tests based on human-readable descriptions and structured plans, and will use a small set of so-called seed samples to get a footing. The research aims at the two most frequent pain points, C firmware-level sanity checks at an early stage, and full System Verilog/UVM at an advanced stage of simulation. Its underlying innovation is specification grounding. The code generated is closely linked to the real hardware bottlenecks by requiring the pipeline to retrieve data directly out of register spreadsheet (XLSX) and IP-XACT maps. In fault tolerance, an integrated repair loop is used to detect compiler errors and dynamically patch the code. Further, an LLM-as-Judge model compares the end result with a specially designed rubric,judging such aspects as whether the intent and truth are aligned or not, and whether the value of true verification is real or not. The empirical analysis of the projects proves a trend of equal, steady improvement in quality. Simple, clear data has been used instead of complex academic measures, making it easier for engineers to directly use it in their work.
Classification of Diabetic Retinopathy and Macular Edema through Segmented Retinal Vessels using Graph Neural Network
(National Institute of Technology, Silchar, 2026) Mutyala, Sukumar Vamsi
Every year, countless people go blind from diabetic retinopathy and macular edema and the tragic reality is that most of them didn’t have to. These conditions can largely be stopped in their tracks, but only if they’re caught early enough, before the damage becomes permanent. That early window depends entirely on a doctor’s ability to see what’s actually going on inside the eye. This is why having accurate, detailed maps of the retina’s blood vessels matters so much. The problem is that current deep learning models tend to fall short in exactly the ways that matter most. They produce broken, incomplete vessel maps missing the tiny capillaries and dropping connections between vessels which are precisely the features a doctor needs to identify the earliest warning signs. To solve this problem, this paper introduces a three stage hybrid framework. It takes three steps to operate the pipeline. First, a dual-encoder graph convolutional network (DE-DCGCN-EE) is used to detect the boundaries of the vessels and model the relationships among the colour channels. Second, a novel VessGAT-SAM2 combination of SAM2 and a Graph Attention Network repairs broken vessel segments, ensures vessel continuity in thin capillaries and generates topologically accurate masks. Third, the multi modal classifier combines the fundus image, the refined vessel mask and the SLIC superpixel maps to predict diabetic retinopathy grade (0-4) and the presence of macular edema. The whole pipeline is trained end-to-end with a joint loss function that reflects the correlation between both conditions. For that purpose, experiments were conducted on four datasets which are publicly available: DRIVE, PRIME-FP20, Messidor-2 and IDRiD. The outcomes were impressive. The overall results were superior to the traditional ones like U-Net, standalone SAM2 and GCN based ones in terms of both accurate segmentation of the vessels and classification of the disease. Most crucially, it remained robust in a variety of datasets, and continued to reveal the fine vessel structures that are important to real clinical significance. This is an exciting step towards the development of automated screening systems, which may help to prevent vision loss due to diabetic eye disease.
Comprehensive Analysis of SoC Physical Design Quality with Timing, Power Integrity, and PVT Variability Considerations
(National Institute of Technology, Silchar, 2026) Gandhi, Himanshu
Design and Analysis of a Low-Power, Low-Jitter LC Oscillator with Capacitor Bank Tuning for Bluetooth, WiFi Applications
(National Institute of Technology, Silchar, 2026) Bharti, Anupama
Almost every modern device from smartphone and wi-fi router to Bluetooth gadgets we use is based on wireless communication. These devices works on stable and accurate frequency generation which is local oscillator (LO) frequency. At the heart of this local oscillator frequency is the Phase-Locked Loop circuit. The overall performance of PLL is strongly influenced by Voltage controlled Oscillator (VCO), acting as the main component of PLL circuit. The VCO directly impacts various parameters such as phase noise, tuning range, lock time, power consumption, jitter etc. A poorly designed VCO can easily limit the performance of the whole system, while a carefully optimized VCO design can significantly improve the signal quality and robustness of the system. Various techniques are developed to address these challenges while achiving optimized circuit design. This project focuses on design and implementation of a differential LC VCO for Bluetooth and wifi applications in 65 nm CMOS technology using Cadence Virtuoso tool. Starting from the basic concepts of PLL and VCO operation, the report briefly reviews different oscillator types and explains the importance of LC-based VCO which are preferred for RF applications. A concise literature review summarizes several state of the art of PLL and VCO designs, highlighting their frequency range, tuning range, phase noise, power consumption and implementation technology. The VCO uses a complementary cross coupled NMOS–PMOS pair to generate the negative resistance required to cancel tank losses and sustain oscillation. The Channel length optimization technique is employed to improve the vco transconductance ‘gm’ making it sufficient to compensate for the losses in tank. The LC tank is designed around a target frequency around which Bluetooth, wifi, zigbee etc works and the device sizes are choosen to meet the required transconductance and output swing as swing below 600mV leads the oscillation to die out. The design is implemented and simulated in Cadence, and key results such as oscillation frequency, tuning behavior, output swing, power consumption, senstivity ‘KVCO’ variation, and phase noise are analyzed. In this work, the systematic design and optimization of a low-power, low-phase-noise, and low jitter LC based voltage-controlled oscillator (LC VCO) is implemented in 65nm CMOS technology. A dual path tuning topology is implemented to achieve a wide tuning xii range as well as low phase noise. Capacitor bank is designed for coarse tuning path by utilizing a digitally controlled capacitor bank to achieve the required bandwidth of approximately 400MHz with 15 % tuning range and the fine tuning path is employed by by keeping the varactor varactor size small for achieving minimal sensitivity ‘KVCO’. The design is compared with the existing LC VCOs to highlight its advantages. Simulation results demonstrate the improved performance, with a figure of merit(FoM) of 189. Process, Voltage, and Temperature (PVT) variations and Monte Carlo simulations are also performed to check the robustness of the device. Thus, the result conform the design reliability across different conditions. The LC VCO design successfully illustrate the critical trade-off between various performance parameter. This results established a practical methodology for high performance RF synthesizer design with 180nm channel length making it ready for full PLL integration.
Design and Analysis of Eddy Current-Based Non-Contact MEMS Sensor for Detection of Pesticides
(National Institute of Technology, Silchar, 2026) Chhajer, Shivang
Ferroelectric Field Effect Transistor (FeFET) for Embedded Non - Volatile Memory Application
(National Institute of Technology, Silchar, 2026) Kumar, Aman
Miniaturized High-Gain Conformal Ku-Band MIMO Antenna for Biomedical Imaging Applications
(National Institute of Technology, Silchar, 2026) Eshwar, Velavalapalli Hanuman Naga Sai
Multiple Quantum Well-based AlGaN/GaN MOS-HEMTs with Stacked-Gate Dielectric Engineering for High-Power and High- Frequency Applications
(National Institute of Technology, Silchar, 2026) Kumar, Nitish
Patch-based Cascaded Underwater Image Enhancement via HSV-Domain Patch Processing and Full-Resolution RGB Refinement with Heterogeneous Skip Connections
(National Institute of Technology, Silchar, 2026) Gautam, Aditi
Underwater images often suffer from severe degradation due to light scattering, color attenuation, and non-uniform illumination. This paper proposes a cascaded two-stage deep learning framework that combines localized enhancement in the HSV color space with global refinement in the RGB domain. In Stage-1, overlapping 256 × 256 patches are enhanced independently to correct region-specific color and illumination distortions, followed by cosine-based blending for seamless reconstruction. Stage-2 performs full-resolution refinement using a residual learning-based network with multi-scale feature extraction, deep supervision, and channel attention to enforce global consistency and improve perceptual quality. Experimental results demonstrate that the proposed method achieves superior performance in terms of PSNR, SSIM, UIQM, and UCIQE, producing visually coherent images with improved color fidelity and structural preservation. The framework provides an effective and robust solution for underwater image enhancement across diverse degradation conditions.
Physical Design Synthesis and Implementation using Synopsys Fusion compiler
(National Institute of Technology, Silchar, 2026) Vishal
The high rate of semiconductor technology development has greatly complicated the modern integrated circuits and efficient Physical Design methodologies can never be of less importance. As technology nodes scale to a larger scale, issues of interconnect delay, congestion, power integrity and timing violations have emerged to dominate the overall performance of the chips. Conventional ASIC design processes (individually synthesize and physically implement) tend to exhibit poor stage-correlation, resulting in multiple design cycles and longer design cycles. Physical Design synthesis and implementation flow with Synopsys Fusion Compiler, which is a single platform of logical and physical design synthesis in the same optimization engine. It includes the entire ASIC design chain, such as starting with the generated gate-level netlist to the ultimate layout that is to be fabricated. Floor planning, power planning, placement, clock tree synthesis (CTS), routing, and timing closure are examined in detail to learn how they affect the quality of designs. Considerable focus is on physical-aware synthesis and early synthesis optimization, which are useful to minimize timing difference between pre-layout and post-layout phases. Several optimization schemes, such as cell sizing, buffering and the congestion-based placement, are investigated to balance timing closure and performance improvements. The integrated solution also quite reduces the repetition of Engineering Change Orders (ECOs), the design cycles and enhances the general productivity as well.The outcomes show that with Fusion Compiler, Quality of Results (QoR) in terms of timing, power and area is improved and convergence.
PIN Diode Based Frequency Reconfigurable U-Slot Microstrip Patch Antenna for Multiband Microwave Communication
(National Institute of Technology, Silchar, 2026) Shankar, Priyanka
This thesis shows the design and analysis of a frequency reconfigurable microstrip patch antenna with a U-slot and an adjusent vertical slot with PIN diode switching. The antenna is fabricated on Rogers RT/duroid 5880 substrate and simulated using ANSYS HFSS. The introduction of the U-slot along with the vertical slot creates multiple current paths on the patch, resulting in the excitation of multiple resonant modes. The effective current distribution can be tuned by switching elements i.e. by equivalent RLC circuits, to obtain the frequency reconfigurability. This antenna operates at multiple resonant frequencies in the range of 6 GHz to 14 GHz covering bands of C-, X- and Ku-bands. The antenna has good impedance matching at these operating bands with return loss values below −10 dB and attained a maximum gain between 5–9 dB. A parametric study has also been performed to study the effect of the dimensions of the slots and patch parameters on the performance of the antenna. This allows to control the tuning of the resonant frequencies. The proposed antenna is suitable for satellite communication applications, such as fixed satellite service (FSS) uplink in the C-band (6.9–7.1 GHz) and Ku-band (13–14 GHz) frequency ranges. Besides the main application in satellite systems, the antenna can also be used in X-band radar and terrestrial microwave backhaul links due to the multi-band operation. The design exhibits a balance between compactness, reconfiguration and practical usage in modern RF communication systems
Predictive TCAD Modelling and Experimental Calibration of FeFET Memory Window for 3D V-NAND Integration
(National Institute of Technology, Silchar, 2026) Singh, Abhiyant
The increasing computational demands of IoT and AI platforms require memory technologies that deliver high density, low power consumption, and strong reliability. While conventional charge-trap NAND has been the workhorse for data storage over last decade, is now facing challenges in terms of process complexity and reduced gate control. Aggressive Z-pitch scaling in vertical NAND (V-NAND) has led to issues such as lateral charge movement resulting in cell-to-cell interference and retention degradation. To enable further scaling opportunities in V-NAND, ferroelectric 𝐻𝑓𝑂₂-based gate stacks has been explored as a potential alternative for charge trap layer. In this regard, novel gate stack engineering approaches using ferroelectrics have already been able to meet up the memory window requirement of next generation NAND. However, despite experimental demonstration of TLC and QLC like MW in FeFET, the underlying mechanism that lead to MW more than theoretical limit is still not explored widely. In this project, we aim to develop a comprehensive TCAD based model to explain the MW observed in FeFET. The MW predicted using this TCAD Model will be then calibrated against experimental results. Finally, we will perform a design space exploration of FeFET Memory Window for 3D V-NAND Integration. In this project, we have investigated FeFETs with three different gate stack configurations, namely 𝑇𝑖𝑁/ 𝐻𝑓𝑂₂/ 𝑆𝑖𝑂₂/𝑆𝑖, 𝑇𝑖𝑁/ 𝐻𝑓𝑂₂/𝐴𝑙ଶ𝑂ଷ/ 𝐻𝑓𝑂₂/ 𝑆𝑖𝑂₂/𝑆𝑖 and 𝑇𝑖𝑁/𝐴𝑙ଶ𝑂ଷ/ 𝐻𝑓𝑂₂/ 𝑆𝑖𝑂₂/𝑆𝑖 and simulated their characteristics such as drain current voltage (𝐼஽ − 𝑉ீ), memory window, electric field distribution, energy band diagram, etc. The simulated FeFET under the assumption of ideal case, demonstrate MW 4.2 V, 3.3 V, 3 V respectively. To study the practical device, the role of interface screening charges were taken into account revealing that Insulating screening charges 𝑄ூ௅ degrade the MW while the Gate blocking screening charges 𝑄ீ஻ tends to enhances the MW. If 𝑄ீ஻ > 𝑄ூ௅ a MW beyond the ideal baseline is achieved. Overall, the results obtained in this study give us a clearer picture of observed MW in FeFET and highlight the role of a detailed TCAD model for accurately predicting and optimizing FeFET behavior for future 3D V-NAND technologies.
Quantum Well Engineered AlGaN/GaN HEMTs for Emerging Nanoelectronics Applications
(National Institute of Technology, Silchar, 2026) Kar, Padmakshya
SCAPS-ML Integration for Double Perovskite Solar Cell Device Optimization: A Multi-Parameter Framework
(National Institute of Technology, Silchar, 2026) Toppo, Ambuj
Study and Analysis of Wideband and Multiband Monopole Antennas on Jeans Textile Substrate
(National Institute of Technology, Silchar, 2026) Basumatary, Bidisha
This thesis presents the design, simulation, and analysis of two wearable monopole antennas developed on a jeans textile substrate for wireless communication applications. The work is divided into two main designs, each targeting different frequency bands. The first design is a wideband antenna operating from 3.75 GHz to 5.85 GHz, covering sub-6 GHz, WLAN, and ISM bands, using a modified T-shaped patch with a partial ground plane and circular DGS slots. It was fabricated and tested, achieving a peak gain of 4.6 dBi and efficiency above 80%.The second design is a compact triple-band antenna resonating at 4.15 GHz, 7.53 GHz, and 10.68 GHz, covering C-band, X-band, and Ku-band, using a symmetrical loop-loaded structure with a comb-shaped DGS. It achieved a peak gain of 6.6 dBi and efficiency above 80% across all bands. Both antennas were designed and simulated using ANSYS HFSS and evaluated in terms of reflection coefficient, gain, efficiency, radiation pattern, and surface current distribution. The first antenna was also experimentally validated. The results confirm that jeans textile substrate is a suitable choice for wearable wideband and multiband wireless communication applications.
Temporal Instability Forecasting for Early Operational Risk Prediction in Railway Systems
(National Institute of Technology, Silchar, 2026) Sourabh, Shreyansh
Railway dispatch systems already log nearly everything that goes wrong on a network. Delays, cancellations, the cause text of each incident, all of it sits in the database. What is a bit odd is that none of this gets rolled up into a single number that tells an operator how stressed the system actually is. Most action happens only after a disruption is big enough for passengers to feel it, and there isn’t really a clean way to look a few weeks ahead. This work tries to fill that gap. It proposes the Operational Instability Index (OII), a bounded weekly score in [0, 1], built from the openly available Belgian Railway incident data between January 2019 and January 2026 (891 records spread across 318 weeks). The OII is put together from six Min-Max normalised features: weekly incident frequency, total delay minutes and cancellation counts, plus the deviation of each from an eight-week rolling baseline. The two groups are then added as a weighted sum, with the absolute components carrying weight 1.0 and the deviation components 0.5. We chose lower weights for the deviations because that series is clearly noisier. An exponential moving average is then applied; without smoothing the lag-1 autocorrelation of the series is very low and forecasting is more or less hopeless. Before fitting anything, a natural log transform is used to cut the right skew (skewness drops from 1.91 to 0.67), and both ADF and PP tests confirm stationarity, so no differencing was needed. Four classical time-series models, ARIMA, SARIMAX with Fourier harmonics, Facebook’s Prophet, and Holt-Winters exponential smoothing, were trained on 253 weeks and evaluated using a rolling one-step-ahead scheme on a 65-week held-out window. An inverse-RMSE weighted ensemble of the four reaches RMSE = 0.0319 and MAPE = 17.57% on the original OII scale. That is the best of every configuration we tried, although the margin over the individual SARIMAX and ARIMA fits is small (and not statistically significant under the Diebold–Mariano test). The forecasts are then mapped into a three-tier probabilistic early warning scheme (Critical, High, Elevated, Low) using percentile thresholds derived only from the training period, to avoid any leakage. The result is a simple, interpretable instrument that hands operators a twelve-week probabilistic outlook on operational health, instead of yet another post-mortem after a bad week.
Variability Analysis of Metal Gate Work Function on Electrical Parameters for Nanosheet FET: A Statistical Simulation
(National Institute of Technology, Silchar, 2026) Ranjan, Ritik
Over the last few decades, to increase the performance of the transistor, the size of the transistor has been reduced rapidly. It adversely affect the switching speed of the processor, but at the cost of degraded performance of traditional FETs. To scale the devices without degrading the performance, a new structure in which the gate covers all sides of the channel is reported, i.e., called a gate-all-around (GAA), but Nanosheet FETs (NSFETs) show good performance. This thesis shows a comprehensive analysis of DC and AC analysis of NSFETs with work function variability using 3D TCAD Sentaurus simulations, with a specific focus on metal-gate work function variability (WFV) and its effects on device reliability and circuit performance. Here, we have used TiN as a gate material with work function values of 4.4 and 4.6 eV in orientation <100> and <111> with probabilities of 40% and 60%, respectively, to study its effect on electrical parameters. The DC analysis, like VT, ION, and IOFF, shows good improvement over FinFETs. The VT of the NSFETs is 13% lower than that of the FinFETs, with the ON Current increasing drastically by 76% compared to FinFETs. Moreover, the OFF-current of FinFET is also 87% lower than that of NSFET and thus, the switching ratio of NSFET is six times greater than that of FinFET. The effect of WFV of metal gate in NSFET for variation in threshold voltage (σVT), ON-state current (σION), OFF-state current (σIOFF), and switching ratio σ(ION/IOFF) is highlighted for different gate length (Lg), effective width (Weff), and grain sizes (Φ̅). As gate dimensions shrink into the deep- nanoscale, metal-gate granularity (MGG) produces fluctuations in the effective gate work function, which increases the variation in σVT, σION, σIOFF, and σ(ION/IOFF). As Φ̅ grows, the fluctuations in electrical parameters increase for different NSFET device dimensions. Results reveal that when Φ̅ is comparable to device dimensions, the variability of electrical parameters gets saturated. Furthermore, the transfer curve of 200 simulated devices and nominal values is plotted at different grain sizes. It is visualised that there are significant variations in drain current as Φ̅ is changed from 2 to 15 nm. The variability of all Analog/RF parameters like σgm, σCgg, σgds, σfT, and σAV decreases with increasing channel length and is reduced for small grain size (Φ̅). With an increase in fin width, the variability of Analog/RF parameters increases, which further degrades with increased grain size. Moreover, it is seen that the cut-off frequency and intrinsic gain are constant and decrease steeply with increasing fin width at different grain sizes.

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