Application of Generative AI in Automated and LLM-Judged C/SystemVerilog/UVM Test Code Generation

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dc.contributor.authorGangrade, Kaustubh
dc.date.accessioned2026-09-22T10:22:12Z
dc.date.available2026-09-22T10:22:12Z
dc.date.issued2026
dc.description.abstractThe engineering of modern VLSI systems-on-chip is becoming increasingly constrained by a single step: verification. This stage is the major cause of schedule delays as well as cost overstretches. Due to the growing use of heterogeneous architecture in chips, the tedious work of writing and maintaining tests has been a major scaling issue. This problem is overcome by the current thesis that produces the pipeline that automates the test case generation. Instead of starting with a blank slate the system will build tests based on human-readable descriptions and structured plans, and will use a small set of so-called seed samples to get a footing. The research aims at the two most frequent pain points, C firmware-level sanity checks at an early stage, and full System Verilog/UVM at an advanced stage of simulation. Its underlying innovation is specification grounding. The code generated is closely linked to the real hardware bottlenecks by requiring the pipeline to retrieve data directly out of register spreadsheet (XLSX) and IP-XACT maps. In fault tolerance, an integrated repair loop is used to detect compiler errors and dynamically patch the code. Further, an LLM-as-Judge model compares the end result with a specially designed rubric,judging such aspects as whether the intent and truth are aligned or not, and whether the value of true verification is real or not. The empirical analysis of the projects proves a trend of equal, steady improvement in quality. Simple, clear data has been used instead of complex academic measures, making it easier for engineers to directly use it in their work.
dc.identifier.urihttp://nits.ndl.gov.in/handle/123456789/114
dc.language.isoen
dc.publisherNational Institute of Technology, Silchar
dc.titleApplication of Generative AI in Automated and LLM-Judged C/SystemVerilog/UVM Test Code Generation
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