Predictive TCAD Modelling and Experimental Calibration of FeFET Memory Window for 3D V-NAND Integration
| dc.contributor.author | Singh, Abhiyant | |
| dc.date.accessioned | 2026-08-20T06:35:11Z | |
| dc.date.available | 2026-08-20T06:35:11Z | |
| dc.date.issued | 2026 | |
| dc.description.abstract | The increasing computational demands of IoT and AI platforms require memory technologies that deliver high density, low power consumption, and strong reliability. While conventional charge-trap NAND has been the workhorse for data storage over last decade, is now facing challenges in terms of process complexity and reduced gate control. Aggressive Z-pitch scaling in vertical NAND (V-NAND) has led to issues such as lateral charge movement resulting in cell-to-cell interference and retention degradation. To enable further scaling opportunities in V-NAND, ferroelectric ðŧððâ-based gate stacks has been explored as a potential alternative for charge trap layer. In this regard, novel gate stack engineering approaches using ferroelectrics have already been able to meet up the memory window requirement of next generation NAND. However, despite experimental demonstration of TLC and QLC like MW in FeFET, the underlying mechanism that lead to MW more than theoretical limit is still not explored widely. In this project, we aim to develop a comprehensive TCAD based model to explain the MW observed in FeFET. The MW predicted using this TCAD Model will be then calibrated against experimental results. Finally, we will perform a design space exploration of FeFET Memory Window for 3D V-NAND Integration. In this project, we have investigated FeFETs with three different gate stack configurations, namely ððð/ ðŧððâ/ ðððâ/ðð, ððð/ ðŧððâ/ðīðāŽķðāŽ·/ ðŧððâ/ ðððâ/ðð and ððð/ðīðāŽķðāŽ·/ ðŧððâ/ ðððâ/ðð and simulated their characteristics such as drain current voltage (ðžāŪ― â ðāŊ), memory window, electric field distribution, energy band diagram, etc. The simulated FeFET under the assumption of ideal case, demonstrate MW 4.2 V, 3.3 V, 3 V respectively. To study the practical device, the role of interface screening charges were taken into account revealing that Insulating screening charges ðāŊāŊ degrade the MW while the Gate blocking screening charges ðāŊāŪŧ tends to enhances the MW. If ðāŊāŪŧ > ðāŊāŊ a MW beyond the ideal baseline is achieved. Overall, the results obtained in this study give us a clearer picture of observed MW in FeFET and highlight the role of a detailed TCAD model for accurately predicting and optimizing FeFET behavior for future 3D V-NAND technologies. | |
| dc.identifier.uri | http://nits.ndl.gov.in/handle/123456789/98 | |
| dc.language.iso | en | |
| dc.publisher | National Institute of Technology, Silchar | |
| dc.title | Predictive TCAD Modelling and Experimental Calibration of FeFET Memory Window for 3D V-NAND Integration |
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