Browsing by Author "Vishal"

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    Physical Design Synthesis and Implementation using Synopsys Fusion compiler
    (National Institute of Technology, Silchar, 2026) Vishal
    The high rate of semiconductor technology development has greatly complicated the modern integrated circuits and efficient Physical Design methodologies can never be of less importance. As technology nodes scale to a larger scale, issues of interconnect delay, congestion, power integrity and timing violations have emerged to dominate the overall performance of the chips. Conventional ASIC design processes (individually synthesize and physically implement) tend to exhibit poor stage-correlation, resulting in multiple design cycles and longer design cycles. Physical Design synthesis and implementation flow with Synopsys Fusion Compiler, which is a single platform of logical and physical design synthesis in the same optimization engine. It includes the entire ASIC design chain, such as starting with the generated gate-level netlist to the ultimate layout that is to be fabricated. Floor planning, power planning, placement, clock tree synthesis (CTS), routing, and timing closure are examined in detail to learn how they affect the quality of designs. Considerable focus is on physical-aware synthesis and early synthesis optimization, which are useful to minimize timing difference between pre-layout and post-layout phases. Several optimization schemes, such as cell sizing, buffering and the congestion-based placement, are investigated to balance timing closure and performance improvements. The integrated solution also quite reduces the repetition of Engineering Change Orders (ECOs), the design cycles and enhances the general productivity as well.The outcomes show that with Fusion Compiler, Quality of Results (QoR) in terms of timing, power and area is improved and convergence.