Modeling and Simulation Of Optimum Stored Charge In Sonos Flash Memory Using Silvaco Tcad
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Date
2022
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Department of Electronics and Instrumentation Engineering, NITS
Abstract
This paper presents the simulation of SONOS memory cells in SILVACO TCAD, varying the thicknesses of the nitride layer from 4 nm to 6 nm. The impact of the nitride layer and tunnel oxide layer thicknesses on the charge distribution in the floating nitride gate are explored, maintaining the gate voltage constant at 16 V. The spatial distribution of trapped electrons is estimated in the floating gate, which fluctuates when the thickness of the nitride layer is changed. For 'logic 0' states, with a 4th order transition time, a fluctuation of 17 % in net charge stored (4.4 10-15 C) is obtained in a 6 nm thick nitride layer. Moreover, a 1.5 nm thick tunnel layer allows 57 % net charge fluctuation in the 'logic 0' state with the 2nd order of transition time. A decrement in net stored charge is found by increasing the tunnel oxide layer thickness from 1.5 nm to 3 nm while keeping the nitride layer constant at 4 nm to 6 nm. The optimised thickness layer of both nitride and tunnel oxide model of SONOS is presented with electron concentration profiles at 'logic 1' and 'logic 0'. Furthermore, the optimised device was regressively studied to analyse threshold voltage and the thickness of the nitride layer varying from 4 nm to 6 nm. This analysis demonstrates the variation in threshold voltage from 3 V to 4.8 V, which is validated with an analytical model. This study evaluates the total net stored charge, the threshold voltage variation, and the data retention for ten years.