Bharti, Anupama2026-08-192026-08-192026http://nits.ndl.gov.in/handle/123456789/97Almost every modern device from smartphone and wi-fi router to Bluetooth gadgets we use is based on wireless communication. These devices works on stable and accurate frequency generation which is local oscillator (LO) frequency. At the heart of this local oscillator frequency is the Phase-Locked Loop circuit. The overall performance of PLL is strongly influenced by Voltage controlled Oscillator (VCO), acting as the main component of PLL circuit. The VCO directly impacts various parameters such as phase noise, tuning range, lock time, power consumption, jitter etc. A poorly designed VCO can easily limit the performance of the whole system, while a carefully optimized VCO design can significantly improve the signal quality and robustness of the system. Various techniques are developed to address these challenges while achiving optimized circuit design. This project focuses on design and implementation of a differential LC VCO for Bluetooth and wifi applications in 65 nm CMOS technology using Cadence Virtuoso tool. Starting from the basic concepts of PLL and VCO operation, the report briefly reviews different oscillator types and explains the importance of LC-based VCO which are preferred for RF applications. A concise literature review summarizes several state of the art of PLL and VCO designs, highlighting their frequency range, tuning range, phase noise, power consumption and implementation technology. The VCO uses a complementary cross coupled NMOS–PMOS pair to generate the negative resistance required to cancel tank losses and sustain oscillation. The Channel length optimization technique is employed to improve the vco transconductance ‘gm’ making it sufficient to compensate for the losses in tank. The LC tank is designed around a target frequency around which Bluetooth, wifi, zigbee etc works and the device sizes are choosen to meet the required transconductance and output swing as swing below 600mV leads the oscillation to die out. The design is implemented and simulated in Cadence, and key results such as oscillation frequency, tuning behavior, output swing, power consumption, senstivity ‘KVCO’ variation, and phase noise are analyzed. In this work, the systematic design and optimization of a low-power, low-phase-noise, and low jitter LC based voltage-controlled oscillator (LC VCO) is implemented in 65nm CMOS technology. A dual path tuning topology is implemented to achieve a wide tuning xii range as well as low phase noise. Capacitor bank is designed for coarse tuning path by utilizing a digitally controlled capacitor bank to achieve the required bandwidth of approximately 400MHz with 15 % tuning range and the fine tuning path is employed by by keeping the varactor varactor size small for achieving minimal sensitivity ‘KVCO’. The design is compared with the existing LC VCOs to highlight its advantages. Simulation results demonstrate the improved performance, with a figure of merit(FoM) of 189. Process, Voltage, and Temperature (PVT) variations and Monte Carlo simulations are also performed to check the robustness of the device. Thus, the result conform the design reliability across different conditions. The LC VCO design successfully illustrate the critical trade-off between various performance parameter. This results established a practical methodology for high performance RF synthesizer design with 180nm channel length making it ready for full PLL integration.en